A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formula tion. Given a SoC integrated with a set of functions and a set of performance fa ctors, a core for each function is selected from a set of alternative IP cores and software components, and optimal partitions is found in a way to evenly bala nce the performance factors and to ultimately reduce the overall cost, size, pow er consumption and runtime of the core-based SoC. The algorithm formulates IP c ores and components into the corresponding mathematical models, presents a graph -theoretic model for finding the optimal partitions of SoC design and transform s SoC hardware/software co-synthesis problem into finding optimal paths in a we ighted, directed graph. Overcoming the three main deficiencies of the traditiona l methods, this method can work automatically, evaluate more performance factors at the same time and meet the particularity of SoC designs. At last, the approa ch is illustrated that is practical and effective through partitioning a practic al system.
