In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.
CAO Kunyong YU Shenglin(College of Automation Engineering,Nanjing University of Aeronautics and Astronautics Nanjing 210016 China)
Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.
