An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.
An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.
