Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.
Using three-dimensional technology computer-aided design （TCAD） simulation, parasitic bipolar amplification in a single event transient （SET） current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both ]30-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.
The effect of p-well contact on the n-well potential modulation in a 90 nm bulk technology with P+ deep well is studied based on three-dimensional (3-D) TCAD device simulations. Simulation results illustrate that the p-well contact area has a great impact on the n-well potential modulation and the enhancement factor will level out as the p-well contact area increases, and that at the same time the increase of p-well doping concentration can also enhance the n-well potential modulation. However, the effect of p-well contact location on the n-well modulation is not obvious as the p-well contact distance increases. According to our simulation results, it is proposed that the p-well contact area should be cautiously designed to mitigate single event effect (SEE) in the P+ deep well technology.
As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.
The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology,thus affecting the propagated single event transient(SET) pulsewidths in circuits.The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range.The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current,and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.
In this paper, compared with two-transistor (2T) inverter chain, the production and propagation of P-hit single event transient (SET) in three-transistor (3T) inverter chain is studied in depth based on three-dimensional numerical simulations in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The pulse attenuation effect is found in 3T inverter chain, and the pulse can not completely propagate through the inverter chain as LET increases. The discovery will provide a new insight into SET hardened design, the 3T inverter layout structure (or similar layout structures) will be a better method in integrated circuits (ICs) design in radiation environment.
