A 10-bit single-slope analog-to-digital converter (ADC) for time-delay-integration CMOS image sensor was proposed. A programmable ramp generator was applied to accomplish the error calibration and improve the linearity. The ADC was fabricated in a 180 nm 1P4M CMOS process. Experimental results indicate that the differential nonlinearity and integral nonlinearity were 0.51/-0.53 LSB and 0.63/-0.71 LSB, respectively. The sampling rate of the ADC was 32 kHz.
A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.
Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 #m CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.
A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and -51.24 dB to 56.53 dB and -54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.
The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor chan- nel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through （APT） implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode （PPD） are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/10^4 to 1/10^7, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.
An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed,which adds signals in the charge domain in the pixel array.A two-shared pixel structure adopting two-stage charge transfer is introduced,together with the rolling shutter with an undersampling readout timing.Compared with the conventional TDI addition methods,the proposed scheme can reduce the addition operations by half in the pixel array,which decreases the power consumption of addition circuits outside the pixel array.The timing arrangement and pixel structure are analyzed in detail.The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity,therefore the power consumption of the periphery addition circuits can be reduced by half theoretically.
