Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.
High-temperature annealing of the atomic layer deposition （ALD） of Al2O3 films on 4H-SiC in O 2 atmosphere is studied with temperature ranging from 800℃ to 1000℃. It is observed that the surface morphology of Al2O3 films annealed at 800℃ and 900℃ is pretty good, while the surface of the sample annealed at 1000℃ becomes bumpy. Grazing incidence X-ray diffraction （GIXRD） measurements demonstrate that the as-grown films are amorphous and begin to crystallize at 900℃. Furthermore, C–V measurements exhibit improved interface characterization after annealing, especially for samples annealed at 900℃ and 1000℃. It is indicated that high-temperature annealing in O2 atmosphere can improve the interface of Al2O3 /SiC and annealing at 900℃ would be an optimum condition for surface morphology, dielectric quality, and interface states.
