A novel dual gate oxide （DGO） process is proposed to improve the performance of high voltage CMOS （HVCMOS） devices and the compatibility between thick gate oxide devices and thin gate oxide devices. An extra sidewall is added in this DGO process to round off the step formed after etching the thick gate oxide and poly-silicon. The breakdown voltages of high voltage nMOS （HVnMOS） and high voltage pMOS （HVpMOS） are 168 and - 158V, respectively. Excellent performances are realized for both HVnMOS and HVpMOS devices. Experimental results demonstrate that the HVCMOS devices work safely at an operation voltage of 100V.
Partially-depleted silicon-on-insulator（PDSOI）floating-body（FB）nMOSFETs and H-gate type body-contacted（BC）nMOSFETs are fabricated with different back channel implantation dosages. The off-state breakdown characteristics of these devices are presented. The off-state breakdown voltages of the FB nMOSFETs increase from 5.2 to 6. 7V, and those of the H-gate type BC nMOSFETs decrease from 11.9 to 9V as the back channel implantation dosages increase from 1.0 ×10^13 to 1.3×10^13 cm^-2. By measuring the parasitic bipolar transistor static gain and the breakdown characteristics of the pn junction between the drain and the body, the differences between the breakdown mechanisms of the FB and H-gate type BC nMOSFETs are analyzed and explained qualitatively.
Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.
